1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same, and more particularly to a structure of CMOS transistors and power MOS transistors and method of manufacturing the same.
2. Description of the Related Art
There have been well known CMOS (Complementary MOS) transistors, each of which is composed of a PMOS transistor and an NMOS transistor. In most of the CMOS transistors, the gate drive voltage is equal to the breakdown voltage, that is, a voltage applicable to the drain when reverse-biased.
On the other hand, a drift region may be formed in the CMOS transistor for achieving a middle/higher breakdown voltage. In addition, a lower gate drive voltage than the breakdown voltage may be applied to control the device. This is effective to achieve enhanced device performances, lowered power, lowered parasitic capacities and lowered on-resistances for achieving faster switching. For that purpose, there have been developed power MOS transistors such as a DMOS (Double diffused MOS) transistor. The power MOS transistor is operative to deplete the drift region to ensure the breakdown voltage.
In recent years, fine processes and fine design rules similar to those for the CMOS transistors, such as a 0.35 μm-rule and a 0.18 μm-rule, have been applied increasingly to the power MOS transistors as well. The application of fine design rules leads to realization of short-channel power MOS transistors and low-voltage-driven power MOS transistors. In such the case, circuitry designs of fine CMOS transistors and power MOS transistors both formed in one chip may be achieved possibly.
On the other hand, as each region becomes finer, a mask misalignment influences more seriously. In a fine process, a mask alignment with high accuracy to meet the requirement must be executed. Nevertheless, it is impossible to eliminate mask misalignments completely. Therefore, finer designs may increase the regions influenced by the mask alignment accuracy. For example, the more design margin needs to be estimated.
There has been devised a low-breakdown voltage power MOS transistor in which a drift region is formed through ion implantation with a mask of a sidewall formed around the gate electrode. In this case, a sidewall thickness of about 0.2 μm (that is, a lateral width of the sidewall) may be required to hold a 5V static breakdown voltage. A drift region having such the length is depleted to ensure the breakdown voltage of the device.
On the other hand, when a conventional method is used to manufacture a semiconductor device comprising CMOS transistors and power MOS transistors in one substrate, the thickness of the sidewall in the power MOS transistor is made equal to the thickness of the sidewall in the CMOS transistor. The sidewall thickness in the CMOS transistor may be applied to the power MOS transistor as it is. In such the case, however, as thin a CMOS sidewall thickness as about 0.1 μm can not achieve a desired static breakdown voltage and causes a restraint on structural designs.
Conventional technologies for forming two types of semiconductor devices having different sidewall thicknesses in combination on the same substrate include one that forms high-breakdown voltage CMOS transistors and low-breakdown voltage CMOS transistors at the same time (for example, JP 2004-349377A).
There is another technology of forming PMOS transistors and NMOS transistors having different sidewall thicknesses in combination on the same substrate (for example, JP 2004-349372A).
However, the method of forming CMOS transistors and low-breakdown voltage power MOS transistors in one substrate needs more progress and developments.